1. Field of the Invention
The present invention relates to non-volatile memory cell arrays, and more particularly to cross-point memory arrays storing more than one bit of information in each memory cell.
2. Description of the Related Art
Non-volatile memory arrays have found widespread use in many commercial and consumer devices. For decades, engineers have sought ways to increase the density and reduce the cost of such devices. Historically, these efforts have resulted in the use of larger numbers of layers, each with smaller and smaller feature sizes, to squeeze more and more bits of memory onto a single integrated circuit. Certain memory devices include more than one memory plane to help increase the density and/or lower the cost per bit.
Such cost-reduction efforts also include increasing the number of bits stored in each memory cell. Memory cells capable of storing 2 or more bits of information are frequently called “multi-level” memory cells, because typically such memory cells are programmed by changing a particular device characteristic to a desired one of many different analog levels, such as a transistor threshold voltage, or a value of resistance. For example, a memory cell having four different programmable values of resistance, or four different programmable values of threshold voltage, can store 2 bits of information.
Multi-level memory cells have been achieved in using a floating gate transistor memory cell structure, and also using transistors incorporating charge storage dielectric material, such as SONOS, in a traditional two-dimensional (2D) memory array using single crystal transistors formed in a semiconductor substrate, and also in a more advanced three-dimensional (3D) stackable memory array using thin-film transistors formed in one or more layers above a semiconductor substrate. However, such memory cells are three terminal devices, which limits the density that is achievable because three wires must be routed through the array and reach each memory cell, or such memory cells must be configured in a series arrangement (e.g., NAND flash memory arrays).
Cross-point arrays have also been fabricated that store multiple bits within a single memory cell. Some of these multi-level memory cells include a single element which is tuned to a particular value of resistance. In U.S. Pat. No. 6,490,218 to Vyvoda, et al., a multi-level memory cell is described which includes a single antifuse whose resistance is “tunable” to several different values of resistance. In U.S. Patent Publication No. 2007-0002603 by Cleeves, a multi-level memory cell is described which includes a single antifuse which is “popped” in a reverse direction, and then tuned in a forward direction to a particular value of resistance. In U.S. Patent Publication No. 2007-0090425 by Kumar, et al., a multi-level memory cell is described which includes a single polysilicon resistor element (PVM) which is tuned to a particular value of resistance. In U.S. Patent Publication No. 2006-0250837 by Herner, et al., a multi-level memory cell is described which includes a single reversible NiOx element. Multiple bits are stored into a single variable resistor material by writing that one resistor material at different currents or voltages. Programming is achieved by applying a programming pulse, checking the resistance achieved, and re-pulsing the cell to “tune” the memory element to a particular value of resistance.
Other multi-level memory cells include two elements, one of which may be tuned to a particular value of resistance. In U.S. Patent Publication No. 2007-0228359 by Herner, a multi-level memory cell is described which includes an antifuse and a single reversible resistance change material. In U.S. Patent Publication No. 2007-0072360 by Kumar, et al., a multi-level memory cell is described which includes an antifuse and a single NiOx element, and achieves a partially OTP and partially re-writable memory cell. In U.S. patent application Ser. No. 11/864,870 filed on Sep. 28, 2007 by Herner, et al., a multi-level memory cell is described which includes two antifuses with different programming characteristics. Each of the antifuses is one-time-programmable, as the resistance of each antifuse decreases with each additional programming pulse. One particular combination includes a first very leaky antifuse, and a second very resistive antifuse, so that a programming voltage may be developed across one antifuse while the other antifuse is unprogrammed.
Each of these known two-terminal multi-level memory cells either makes use of careful tuning of a single memory element, and/or includes an antifuse that renders at least one of the bits stored therein one-time-programmable (i.e., non-rewritable).